1. Technical Field of the Invention
The invention relates generally to the field of integrated circuits and, more particularly, to via structures in integrated circuits.
2. Description of Related Art
Over the last few decades, the electronics industry has developed semiconductor technology to fabricate small, highly integrated electronic devices. Much of recent technological progress embraces the increasing miniaturization afforded by advances in integrated circuit processing technology. Dramatic improvements in the circuit density available on individual integrated circuit chips have been made.
Many semiconductor devices are now formed by vertical stacking of device layers, including multiple layers of conductive lines with interconnects between the layers. These conductive lines and interconnects are typically formed using metals, including, for example, aluminum, tungsten, and copper.
In a multilevel architecture, layers of conductive lines which define circuit pathways are separated from each other by interlevel dielectrics. In a typical fabrication of a modern semiconductor device, a first conductive layer is deposited and patterned over a semiconductor surface. Then, a layer of dielectric, such as silicon dioxide, is deposited over the patterned conductive layer. Typically, the silicon dioxide is planarized to provide a flat surface. The planarized dielectric is then patterned to form vias. Vias are holes through the dielectric used for interconnecting the different conductive layers of the semiconductor circuit. The vias are filled with a conductive material such that another layer of conductive material can be deposited over the vias and the dielectric to provide an upper conductive pattern. Copper has become the preferred via material because of its excellent conductivity and current capacity, however copper requires a distinct adhesive layer, such as chromium, to bond the copper to the dielectric. For this reason, aluminum is sometimes used because it readily bonds with dielectrics without an intermediate adhesive layer.
Subsequent conductive layers are deposited over corresponding dielectric material layers which are provided with corresponding vias to form an interconnect pattern for an integrating circuit.
Generally, on the periphery of such integrated circuits, very large areas are etched in the silicon dioxide to form bond pads. Vias are also used in the formation of the bond pads which are typically used to interconnect, for example, wire bonds to an integrated circuit. These bond pad vias are also filled with a conductive material such that the wire bonds can be coupled over the vias to provide a conductive coupling to the chip.
Typically, integrated circuit chips are individually packaged and the packages are mounted on printed circuit boards. The sizes of the packages limit chip density on the printed circuit board, requiring larger systems and limiting overall circuit performance due to longer inter-chip connections. More recently, multi-chip carriers have been developed which permit multiple integrated circuit chips to be mounted on a common carrier without the need for packaging the individual chips. This allows the chips to be packed more closely together.
While multi-chip carriers have been fabricated using a variety of technologies, the greatest chip density has been achieved by multi-chip carriers fabricated using the above-mentioned integrated circuit processing technology. In other words, a multi-chip carrier can be fabricated by defining multiple layers of circuits interconnected by metal vias through intermediate dielectric layers. Individual integrated circuit chips are attach to the upper layer of the multi-chip carrier and transceive electrical signals through the multi-chip carrier's circuit layers and vias.
High conductivity of the interconnects of the conductive layers of an integrated circuit and bonding of the integrated circuit is important for the efficient operation of such a circuit, particularly at submicron technologies. One of the problems with typical via structures, particularly with wire-bond pads, is poor bondability due to size reduction and lack of rigidity associated with conventional via arrangements. The connection between the pad and the bonding wire is performed by “wire bonding”, which connects metal materials by pressing one to the other while using pressure, heat and ultrasonic vibration simultaneously. A copper or gold wire, for example, supplied through a capillary is balled by heating and the ball is pressed and connected to the pad while applying ultrasonic vibration.
When the wire is mechanically pressed to the pad in order to perform the thermosonic wire bonding, there is a possibility that the pressing force is propagated to a connecting portion between the pad and the underlying layer where the connecting portion can be damaged. This phenomenon does not cause a substantial problem if the size of the pad is relatively large. However, when the size of the pads are reduced with reduction of the size of semiconductor element and increase of the integration density, the size of the ball formed on the top of the wire must be reduced. Therefore, stress exerted on a unit area of the pad is increased, so that breakage and damage of the pad and the underlying insulating film tend to occur. This problem may cause the pad to be easily torn, resulting in reduction of fabrication yield of semiconductor device.
An improved via structure which enhances the rigidity of the structure without altering the ratio of via area to total chip area would therefore be advantageous.